The present invention relates to a semiconductor device and a manufacturing method thereof, which can be used for, e.g., the manufacturing of a semiconductor device having MOSFETs in wiring layers.
There is a case where, after an LSI (Large Scale Integration) or the like is designed, a timing delay is detected in signal transmission in the chip of the LSI and redesign is required. The delay is caused by a signal flowing in a long-distance wire and is likely to occur in, e.g., a wire connecting modules such as a memory cell and a CPU (Central Processing Unit) to each other, a wire connecting memory arrays to each other, a lead-out wire from a memory array, or the like. Such a long-distance wire is formed in most cases in the upper one of a plurality of wiring layers stacked over a semiconductor substrate.
As a method of reducing a timing delay, a method has been known which inserts a repeater cell in the middle of a long-distance wire so as to divide the long-distance wire and thus corrects timing.
Patent Document 1 (International Patent Publication No. WO2012/121255) describes the formation of MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) in wiring layers.
Patent Document 2 (Japanese Unexamined Patent Publication No. 2003-45972) describes the replacement of a dummy cell with a repeater cell for timing correction.